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Job Title: Digital Design Staff Engineer View more Digital Design Staff Engineer Jobs Job Code: GW-07291013352246 Salary Range: DOE Job Location: CA Organization: Silicon Image || Research This Company City: Sunnyvale    State: CA JOB DESCRIPTION:
Job Description: ASIC design and verification engineer who is involved in various steps of ASIC design and verification process. Verifies high level architecture of ASIC using high level behavioral modeling in SystemC and/or Verilog Verifies RTL logic design using Verilog Verifies RTL logic design using FPGA emulation Design high level reference model of ASIC and involves in actual RTL coding Design demo and/or reference board for system validation using FPGA emulation Job Requirements: MS + 5 years or BS + 8 years Knowldege and industrial experience on Verilog based ASIC design and verification – MUST HAVE RTL coding in Verilog, RTL verification methodology & tool chain, FPGA based emulation and verification Knowledge and experience on system level modeling using Verilog and/or SystemC Pluses would be experience with HDMI,SATA, and consumer products. Must have good communication skills, be positive and proactive to a given task, and ability to work in team environment.
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